Partcl Launches: Design Chips in Minutes

Partcl recently launched!

‍

^{"GPU Accelerated Electronic Design Automation"}

‍

Founded by Vamshi Balanaga & William Salcedo

‍

Imagine hitting compile and waiting 3 weeks to learn you missed a semicolon... or 5 weeks to catch a runtime error.

Welcome to ASIC life.

They are slashing those weeks down to minutes — so you can build better chips, faster.

‍

🤔 Why did they build this?

During their time at Nvidia and other startups, they found that engineers spend large amounts of the 24 month chip design cycle idle, waiting for runs to finish.

Partcl speeds up Physical Design tools by rearchitecting algorithms for GPUs.

‍

🧑‍💻What it means for designers:

• Quick power, performance, and area estimates
• Fix timing/power bugs in RTL w/out handoff to the PD team
• Build better chips, faster

‍

✅What they have right now:

• 700X faster Static Timing Analysis - enabling super quick performance simulations
• 100X faster Gate Resizing
• 100X faster global and detailed placement

‍

🔜What’s in the pipeline:

• LSP integration for Incremental synthesis - Synthesis as fast as you can type
• Natural Language interface to any intermediate database - Directly query the state of your database with text instead of asking a junior engineer to build you a dashboard

‍

The Ask

Are you building

• AI Accelerators? Partcl brings in tapeout deadlines with faster tools, bringing your chip to market faster!
• Embedded/ IoT devices? Partcl decreases NRE by shrinking design cycles. Decreased NRE directly translates to higher margins.
• Mobile SoCs? Partcl’s physics informed models let you optimize the power-performance tradeoff for your use case.

Email the founders here or here.

Learn More

‍

^{🌐 Visit partcl.com to learn more.}

^‍

^{🤝  Email the founders here to try Partcl and let them know what you think.}

^{⭐ Give Partcl a star on Github.}

^‍

^{👣 Follow Partcl on LinkedIn.}

‍