ArchGen Labs tackles the heat problem inside stacked semiconductor chips

Stacking computing components vertically can shorten the distance data travels. It also makes heat harder to remove. ArchGen Labs is building design software around that trade-off, helping engineers consider chip layout, timing and temperature together before a design reaches manufacturing.

The startup’s most specific early claim concerns thermal analysis. In its launch announcement, ArchGen says its LayerTherm model averaged 62 milliseconds to predict a temperature map, compared with 314 seconds for the conventional solvers used in its benchmark. The roughly 5,000-fold speed comparison is company-reported and applies to that test, rather than every part of chip design.

The intended use is screening: identify promising layouts and likely hotspots quickly enough to examine more possibilities before detailed verification. A fast estimate can change which designs receive an expensive check. It does not, by itself, establish that a chip is ready to manufacture.

Watch ArchGen Labs’ original launch video.

ArchGen also develops placement software, which determines where components should sit. Its YC profile says the core engine placed first in Hudson River Trading’s macro-placement challenge. The company presents that result as evidence for its design approach, although performance in a particular challenge is a narrower claim than superiority across chip designs.

A third product, Newton, applies an AI agent to placement, routing and repairs to design-rule or timing problems. According to the company, it tests proposed changes and carries successful results forward. The aim is to reduce the repetitive iterations between a candidate layout and the checks that determine whether it works.

The physical constraint ties the products together. Moving components closer can improve communication between them, while concentrating computation changes how heat moves through the stack. Optimizing one measure in isolation can leave an engineer with a different problem elsewhere. ArchGen’s pitch is to make those trade-offs visible during design, rather than discover them after too much work has been committed.

Founders Hariharan Ayappane and Naveen Venkat are part of Y Combinator’s Fall 2026 batch. The company says it has signed pilot projects and is working with GlobalFoundries on 3D chip development. Its target is a first tapeout in mid-2027, the point when a completed design is sent for manufacturing.

LayerTherm uses physics-informed neural networks to turn a power-distribution map into a predicted temperature field. The launch’s research graphic shows patterns of heat alongside the input layouts, making the proposed screening step visible. Its caption distinguishes that comparison from a complete three-dimensional integrated-circuit validation. That qualification matters when interpreting an unusually large speedup.

ArchGen is seeking evaluations from physical-design and timing teams, developers of AI accelerators and stacked chips, and engineers working in foundries or advanced packaging. Those groups face different constraints, so a useful pilot would test where the faster feedback fits within an existing design process, not just whether it wins a standalone timing comparison.

That target places the launch at the tooling and pilot stage. The next meaningful evidence will come from designs that move through the full process, including the detailed checks that a quick thermal prediction is meant to help engineers reach.